以第一作者發(fā)表相關(guān)論文15篇。其中，SCI檢索國(guó)際期刊論文11篇，EI檢索期刊論文3篇（含國(guó)內(nèi)權(quán)威期刊《計(jì)算機(jī)研究與發(fā)展》1篇），國(guó)際會(huì)議International  MultiConference of Engineers and Computer Scientists論文1篇：

[1]  Weizheng Wang, Zhuo Deng, Jin Wang. Enhancing Sensor Network Security  with Improved Internal Hardware Design, Sensors, 2019, 19, 1752. (SCI)

[2]  Weizheng Wang, Jincheng Wang, Wei Wang, Peng Liu, Shuo Cai. A Secure  DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks, IEEE  Access, 2019, 7: 22206-22213. (SCI)

[3]  Weizheng Wang, Zhuo Deng, Jin Wang. Securing Cryptographic Chips  Against Scan-based attacks in Wireless Sensor Network Applications, Sensors,  2019, 19, 4598. (SCI)

[4]  Weizheng Wang, Jincheng Wang, Zengyun Wang, Lingyun Xiang.  Access-in-turn test architecture for low-power test application,  International Journal of Electronics, 2017, 104(3): 433~441. (SCI)

[5]  Weizheng Wang, Jincheng Wang, Shuo Cai, Wei Su, Lingyun Xiang.  Compression-friendly low power test application based on scan slices reusing,  Journal of Semiconductor Technology and Science, 2016, 16(4): 463~469. (SCI)

[6]  Weizheng Wang, Cai Shuo, Lingyun Xiang. SOC Test Compression Scheme  Sharing Free Variables in Embedded Deterministic Test environment, Journal of  Semiconductor Technology and Science, 2015, 15(3): 397-403. (SCI)

[7]  Weizheng Wang, Cai Shuo, Lingyun Xiang. Scan Power-Aware Deterministic  Test Scheme Using a Low-Transition Linear Decompressor. International Journal  of Electronics, Vol. 102, No. 4, pp: 651-667, 2015 (SCI)

[8]  Weizheng Wang, Cai Shuo, Lingyun Xiang. Reducing Test Power and  Improving Test Effectiveness for Logic BIST, Journal of Semiconductor Technology  and Science, Vol. 14, No. 5, pp: 640-648,2014. (SCI)

[9]  Weizheng Wang, Liu Peng, Cai Shuo, Lingyun Xiang. Low power logic BIST  with high test effectiveness. IEICE Electronics Express, Vol. 10, No. 23, pp:  1-6, 2013. (SCI)

[10]  Weizheng Wang, Jishun Kuang, Liu Peng, Xin Peng, Zhiqiang You.  Switching activity reduction for scan-based BIST using weighted scan input  data. IEICE Electronics Express, Vol. 9, No. 10, pp: 874-880, 2012. (SCI)

[11]  Weizheng Wang, Jishun Kuang, Zhiqiang You. Achieving low capture and  shift power in linear decompressor-based test compression environment,  Microelectronics Journal, Vol. 43, No. 1, pp: 143-140, 2012. (SCI)

[12]  王偉征,鄺繼順,尤志強(qiáng), 劉鵬. 一種基于掃描子鏈輪流掃描捕獲的低費(fèi)用BIST方法, 計(jì)算機(jī)研究與發(fā)展, 第49卷, 第4 期,  864-872 頁(yè), 2012. (EI)

[13]  Weizheng Wang, Jishun Kuang, Zhiqiang You, Liu Peng. Reducing  Test-Data Volume and Test-Power Simultaneously in LFSR Reseeding-based  Compression Environment, Journal of semiconductors, Vol. 32, No. 7, pp:  075009(1)-075009(7), 2011. (EI)

[14] Weizheng Wang, Jishun Kuang, Zhiqiang You. Low Power  Compression in linear decompressor-based test compression environment.  International Review on Computers and Software, Vol. 6, No. 4, pp: 550-554,  2011. (EI)

[15] Weizheng Wang, Jincheng Wang, Shuo Cai, Peng Liu, Tieqiao  Liu. A Low-Area Overhead Secure Scan Architecture Resisting Scan-Based  Attacks for Crypto Chips, Proceedings of the International MultiConference of  Engineers and Computer Scientists (IMECS 2017), Hong Kong, March 15-17.

7、 所獲學(xué)術(shù)榮譽(yù)及學(xué)術(shù)影響：

1、 中國(guó)計(jì)算機(jī)學(xué)會(huì)會(huì)員

2、 IEEE會(huì)員

3、 擔(dān)任IEEE Access、Electronics  Letters、Microelectronics  Journal等國(guó)際SCI期刊的審稿人