報(bào)告承辦單位:計(jì)算機(jī)與通信工程學(xué)院
報(bào)告內(nèi)容: 2.5D 和 3D 集成電路的可靠性與信號(hào)完整性分析和優(yōu)化
報(bào)告人姓名：彭亞銳
報(bào)告人所在單位:阿肯色大學(xué)計(jì)算機(jī)系
報(bào)告人職稱/職務(wù)及學(xué)術(shù)頭銜:助理教授
報(bào)告時(shí)間:2019年1月3日下午3點(diǎn)
報(bào)告地點(diǎn):理科樓B-311
報(bào)告人簡(jiǎn)介: As a leading contender of more‐than‐Moore technology, 2.5D/3D integrated circuits are built by stacking multiple homogeneous and heterogeneous dies and connecting them with high density inter‐die vias. Such an aggressive integration leads to many‐fold improvement in interconnection length and footprint. The industry now is working relentlessly to build advanced multi‐chip solutions that satisfy the ever‐ demanding memory bandwidth and energy efficiency requirements in datacenter servers, self‐driving automobiles, and low‐power mobile devices. However, the high‐ power devices packed under a small footprint raise various reliability concerns including power delivery, heat dissipation, and noise coupling. In this talk, I will present CAD and design techniques to enhance electro‐power‐thermal reliability of 2.5D and 3D ICs. First, I will introduce a CAD platform that evaluates and optimizes power and thermal reliability for 3D memory cubes and 3D multi‐core processors. Next, I will present various methodologies for extracting and optimizing new parasitic elements in face‐to‐ back and face‐to‐face 3D ICs as well as 2.5D wafer‐level package. I will conclude with my collaborative research with the NSF POETS center at the University of Arkansas on design automation for multi‐chip power electronics. Bio: Yarui Peng received the B.S. degree from Tsinghua University, Beijing, China in 2012. He received his M.S. and Ph.D. in School of Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta, GA in 2014 and 2016, respectively. He joined the Department of Computer Science and Computer Engineering at the University of Arkansas as an assistant professor in 2017 and collaborates with NSF‐sponsored POETS engineering research center on design automation of high‐density power electronics. His research interests are in computer‐aided design, analysis, and optimization for emerging technologies and systems, such as 2.5D Fan‐Out Wafer‐Level‐Packaging, heterogenous 3D ICs, and high‐efficiency VLSI and memory systems. He is also interested in design automation of wide band‐gap power electronics and mobile electrified systems. He is the recipient of best student paper award in ICPT’16 and best paper award in EDAPS’17.
