個(gè)人簡介

吳麗娟，女，博士，教授。2005年于四川大學(xué)取得通信與信息系統(tǒng)的碩士學(xué)位。2012于電子科技大學(xué)取得微電子學(xué)與固體電子學(xué)的博士學(xué)位。2014年7月至今在長沙理工大學(xué)物理與電子科學(xué)學(xué)院工作。主持國家自然科學(xué)基金項(xiàng)目、湖南省自然科學(xué)基金面上項(xiàng)目、湖南省教育廳項(xiàng)目、橫向項(xiàng)目等20余項(xiàng)。以第一作者發(fā)表A類期刊論文30篇，SCI論文50余篇；出版國家“十三五”科學(xué)技術(shù)專著叢書1部；申請發(fā)明專利20余項(xiàng)。

主要研究領(lǐng)域

功率半導(dǎo)體器件與功率集成芯片，集成電路設(shè)計(jì)與制造，微電子系統(tǒng)設(shè)計(jì)封裝與測試。

教學(xué)情況

在本科生及研究生教育教學(xué)工作中系統(tǒng)開設(shè)了6門課程，包括本科生教學(xué)的 4門主干專業(yè)課，分別是《固體物理與半導(dǎo)體物理》、《半導(dǎo)體物理》、《微電子器件基礎(chǔ)》、《微電子工藝學(xué)》，以及研究生教學(xué)的2門專業(yè)基礎(chǔ)課：《半導(dǎo)體功率器件》、《微電子工藝學(xué)基礎(chǔ)》。主持省級(jí)教改-重點(diǎn)項(xiàng)目，共培養(yǎng)碩士研究生50余人。教學(xué)注重漁魚兼受，立德樹人，牽頭獲校級(jí)研究生教育教學(xué)成果二等獎(jiǎng)和思政教學(xué)比賽三等獎(jiǎng)，優(yōu)秀班主任、陽光園丁等榮譽(yù)。

主要學(xué)術(shù)論文

[1]Lijuan Wu Deqiang Yang et al. A novel 4H-SiC IGBT with double gate PMOS for improving the switch controllability and FBSOA [J]. Microelectronics Journal，2024，147：106187.

[2]Wu, Lijuan, Guanglin Yang, Deqiang Yang, Zigui Tu, Jie Yuan, Dongsheng Zhao, Mengjiao Liu, and Jiahui Liang. Self-Clamped P-Shield 4H-SiC Trench MOSFET for Low Turn-off Loss and Suppress Switching Oscillation [J]. Microelectronics Journal，2024，151: 106307.

[3]Wu, Lijuan, Jiahui Liang, Mengyuan Zhang, et al. An Approach for Extracting the Sic/Sio2 Sic Mosfet Interface Trap Distribution and Study During Short Circuit. [J]Materials Science in Semiconductor Processing， 2023: 163.

[4]Wu, Lijuan, Mengyuan Zhang, Jiahui Liang, et al. A Low-Loss 1.2 kV SiC MOSFET with Improved UIS Performance [J].Micromachines, 2023. 14(5): 1061.

[5]Wu, Lijuan，Gang Yang，Mengjiao Liu et al.Multi-dimensional accumulation gate LDMOS with ultra-low specific on-resistance [J].Microelectronics Journal，2023，138：105860.

[6]Lijuan Wu, Mengjiao Liu, Mengyuan Zhang, et.al. Low On-State Voltage and EMI Noise 4H-SiC IGBT With Self-Biased Split-Gate pMOS[J].IEEE Transaction on Electron Device, 2023, 70(2): 647-652.  

[7]Lijuan Wu, Xuanting Song, Banghui Zhang, et.al. Novel Snapback-Free Shorted-Anode SOI-LIGBT With Shallow Oxide Trench and Adaptive Electron Channel[J]. IEEE Transaction on Electron Device, 2023, 70(1): 185-190. 

[8]Lijuan Wu, Tao Qiu, Xuanting Song, et al. Analytical model for high-k SOI pLDMOS with self-adaptive balance of polarization charge[J]. Microelectronics Journal, 2023, 132: 105677.

[9]Lijuan Wu, Banghui Zhang, Gaoqiang Deng, et al. A Superjunction Insulated Gate Bipolar Transistor with Embedded Self-biased N-Type Metal–Oxide–Semiconductor Field-Effect Transistor[J]. Journalof Electronic Materials, 2023: 1-8.   

[10]Lijuan Wu, Qing Liu, Gaoqiang Deng, et al. Improving dynamic performance for split-gate trench power MOSFETs using variable vertical doping profile[J]. Micro and Nanostructures, 2022, 172: 207446.

[11]Lijuan Wu, Heng Liu, Xuanting Song, Xing Chen, Jinsheng Zeng, Tao Qiu, Banghui Zhang.A 4H-SiC Trench IGBT with Controllable Hole-Extracting Path for Low Loss[J]. Chinese Physics B, 2022, 32(4): 48503-048503.

[12]Lijuan Wu, Xing Chen, Jinsheng Zeng, et.al. Novel Accumulation Mode Super Junction Device with Extended Super Junction Gate[J]. IEEE Transaction on Electron Device, 2022, 69(5): 2560-2565.  

[13]Lijuan Wu, Jinsheng Zeng, Xing Chen, et al. Analytical Model and Mechanism of a Linear Extended Gate for Lateral Internal Superjunction Power Devices[J]. Silicon, 2022:1-7.

[14]Lijuan Wu, Shaolian Su, Xing Chen, et al. A deep trench super-junction LDMOS with double charge compensation layer[J]. Journal of Semiconductors, 2022, 43(10): 104102.  

[15]Lijuan Wu, Ye Huang, Yue Song, et al. Novel High-K SOI LDMOS with N+ Buried Layer[J]. IETE Technical Review, 2020, 39(2): 310-315.

[16]Lijuan Wu, Lin Zhu, Xing Chen et al. Variable-K double trenches SOI LDMOS with high-concentration P-pillar[J]. Chinese Physics B, 2020, 29(5): 057701.

[17]Lijuan Wu, Jiaqi Chen, Hang Yang et al. A Ultra?Low Specifc On?Resistance and Extended Gate SJ LDMOS Structure[J]. Transactions on Electrical and Electronic Materials, 2021, 22: 211–216.

[18]Lijuan Wu, Haifeng Wu, Jinsheng Zeng et al. A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance[J]. Silicon, 2021: 1-9.

[19]Lijuan Wu, Qilin Ding, Jiaqi Chen et al. Improved Deep Trench Super junction LDMOS Breakdown Voltage By Shielded Silicon Insulator Silicon Capacitor[J]. Silicon, 2020: 1-6.   

[20]Lijuan Wu, Yiqing Wu, Yinyan Zhang et al. High Voltage Lateral Double Diffused Metal Oxide Semiconductor with Double Superjunction[J].Journal of ELECTRONIC MATERIALS, 2019, 48(4): 1-7.   

[21]Lijuan Wu, Yiqing Wu, Bing Lei et al. PSJ LDMOS with a VK dielectric layer[J]. Micro&Nano Letters,2019:1–4.  

[22]Lijuan Wu, Ye Huang, Yiqing Wu et al. Investigation of the stepped split protection gate L-Trench SOI LDMOS with ultra-low specific on resistance by simulation[J]. Materials Science in Semiconductor Processing, 2019, 101:272-278.

[23]Lijuan Wu, Qilin Ding, Jiaqi Chen et al. A Lateral Double-Diffusion Metal Oxide Semiconductor Device with a Gradient Charge Compensation Layer[J]. Journal of ELECTRONIC MATERIALS, 2019, 48(12):7970-7976.

[24]Lijuan Wu,Yinyan Zhang,Hang Yang et al.Optimization of novel superjunction LDMOS with partial low K layer[J]. Superlattices and Microstructures, 2018, 123:226-233.

聯(lián)系方式

E-mail: 305719669@qq.com

通訊地址:長沙理工大學(xué)(云塘校區(qū))物理與電子科學(xué)學(xué)院理科樓C309